On Sun, Apr 28, 2019 at 4:53 AM Frank Lee <tiny.windzz@xxxxxxxxx> wrote: > > On Sat, Apr 27, 2019 at 5:15 AM Rob Herring <robh@xxxxxxxxxx> wrote: > > > > On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > > > Allwinner Process Voltage Scaling Tables defines the voltage and > > > frequency value based on the speedbin blown in the efuse combination. > > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > > > provide the OPP framework with required information. > > > This is used to determine the voltage and frequency value for each > > > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > > > > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > > > with following parameters: > > > - nvmem-cells (NVMEM area containig the speedbin information) > > > - opp-microvolt-<name>: voltage in micro Volts. > > > At runtime, the platform can pick a <name> and matching > > > opp-microvolt-<name> property. > > > HW: <name>: > > > sun50iw-h6 speed0 speed1 speed2 > > > > We already have at least one way to support speed bins with QC kryo > > binding. Why do we need a different way? > > For some SOCs, for some reason (making the CPU have approximate performance), > they use the same frequency but different voltage. In the case where > this speed bin > is not a lot and opp uses the same frequency, too many repeated opp > nodes are a bit > redundant and not intuitive enough. > > So, I think it's worth the new method. Well, I don't. We can't have every SoC vendor doing their own thing just because they want to. If there are technical reasons why existing bindings don't work, then maybe we need to do something different. But I haven't heard any reasons. Rob
