Hi > > > On Sat, Apr 20, 2019 at 09:12:52AM +0000, Daniel Baluta wrote: > > From: Shengjiu Wang <shengjiu.wang@xxxxxxx> > > > > SAI has 4 clock sources, which can be selected using MSEL bit of SAI > > TCR2 register. > > I have a doubt at this statement. As far as I can understand, this MSEL is > probably used by its internal clock MUX, so it's not really proving that SAI > has 4 MCLK inputs. What I know is that SAI block itself only has 3 MCLK > inputs as we defined in DT. It's just internally connects bus clock or MCLK1 > to input0 of clock MUX's and connects MCLK[1-3] to input[1-3]. So adding an > MCLK0 here doesn't sound a right way to me. Unless someone can justify > for it, I think we should just fix it from driver side. > > Thanks > Nicolin > The MSEL bit width is 2 bit, so there is 4 options, the MCLK0 maybe the same input as MCLK1 or bus clock as you said, so we think may be better to show this relation in DT, And this is DT's capability. Driver don't care about which clock connect to MCLK0, it only need to know there is 4 MCLK from DT. Best regards Wang shengjiu
