On Thu, Apr 03, 2014 at 03:42:00PM +0000, David Laight wrote: > From: Russell King - ARM Linux > > DMA coherent memory is write combining, so multiple writes will be > > coalesced. This also means that barriers may be required to ensure the > > descriptors are pushed out in a timely manner if something like writel() > > is not used in the transmit-triggering path. > > You also have to ensure that the write that changes the 'owner' > bit is the one that happens last. > > If (for example) a descriptor has two words, one containing the > buffer address and the other containing the length and flags, > then you have to absolutely ensure that the hardware will not > read the new 'flags' with the old 'buffer address'. > Any write to tell the hardware to look at the tx ring won't > help you - the hardware might be reading the descriptor anyway. > > Even if the accesses are uncached, you need the appropriate > barrier (or volatiles) to stop gcc reordering the writes. > (I think accesses to volatiles can't be reordered - check.) Exactly... I wish Freescale were as thoughtful as you are on this point. :) -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
