From: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx> The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU general register files to know the DRAM type, so add a phandle to the syscon that manages these registers. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx> Reviewed-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> Acked-by: Rob Herring <robh@xxxxxxxxxx> Signed-off-by: Gaël PORTAY <gael.portay@xxxxxxxxxxxxx> Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx> --- Changes in v4: - [PATCH v3 2/5] Add Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>. Changes in v3: - [PATCH v2 2/5] Add Signed-off-by: Gaël PORTAY <gael.portay@xxxxxxxxxxxxx>. Changes in v2: None Changes in v1: - [RFC 2/10] Add reviewed and acked tags from Chanwoo Choi and Rob Herring Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index 0ec68141f85a..951789c0cdd6 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -12,6 +12,8 @@ Required properties: for details. - center-supply: DMC supply node. - status: Marks the node enabled/disabled. +- rockchip,pmu: Phandle to the syscon managing the "PMU general register + files". Optional properties: - interrupts: The CPU interrupt number. The interrupt specifier -- 2.21.0
