On Thu, 20 Dec 2018, Rob Herring wrote: > On Fri, Dec 14, 2018 at 09:21:54PM -0800, Paul Walmsley wrote: > > Add initial board data for the SiFive HiFive Unleashed A00. > > > > Currently the data populated in this DT file describes the board > > DRAM configuration and the external clock sources that supply the > > PRCI. ... > > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts > > new file mode 100644 > > index 000000000000..0c6afabe69e3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts > > @@ -0,0 +1,39 @@ > > +// SPDX-License-Identifier: Apache-2.0 > > +// SPDX-License-Identifier: GPL-2.0-or-later > > This should be a single line with: (Apache-2.0 OR GPL-2.0+) Done. > > + model = "SiFive HiFive Unleashed A00 (FU540-C000)" > > + compatible = "sifive,hifive-unleashed-a00-fu540", > > + "sifive,hifive-unleashed-fu540"; > > SoC compatible should be here too. Done. > > + soc { > > + hfclk: hfclk { > > + #clock-cells = <0>; > > + compatible = "fixed-clock"; > > + clock-frequency = <33333333>; > > + clock-output-names = "hfclk"; > > + }; > > + rtcclk: rtcclk { > > + #clock-cells = <0>; > > + compatible = "fixed-clock"; > > + clock-frequency = <1000000>; > > + clock-output-names = "rtcclk"; > > + }; > > Are these the clock inputs to the SoC or dummy clocks until you write a > proper clock driver? If the former, they should be at the top level. Done. Thanks for your comments; Will send an updated patch set. - Paul