On Thu, Apr 4, 2019 at 6:17 AM Will Deacon <will.deacon@xxxxxxx> wrote: > > Hi Frank, > > On Fri, Feb 15, 2019 at 06:03:11PM +0000, Frank Li wrote: > > Add ddr performance monitor support for iMX8QXP > > > > There are 4 counters for ddr perfomance events. > > counter 0 is dedicated for cycles. > > you choose any up to 3 no cycles events. > > > > for example: > > > > perf stat -a -e ddr0/read-access/,ddr0/write-access/,ddr0/precharge/ ls > > perf stat -a -e ddr0/cycles/,ddr0/read-access/,ddr0/write-access/ ls > > Could you elaborate a bit on DDR_CAP_AXI_ID, please? Specifically, how > does the COUNTER_DPCR1 register work and what happens if I specify two > simultaneous events with different values in config1? I'm a little wary > of taking raw user input and throwing it straight into a device register! I have not find better method to do that. bit 0-15: AXIID bit 16-31: AXID_MASK Check condition AxID && AXI_MASKING == AXI_ID && AXI_MASKING best regards Frank Li > > Will
