On Thu, Feb 21, 2019 at 06:24:51PM +0000, Aisheng Dong wrote:
> MX8 SoC is comprised of a few HW subsystems while some of them can be
> reused in the different SoCs. So let's re-orginize them into subsystems
> in device tree as well for the possible reuse of the common part.
>
> Note, as there's still no devices of hsio subsys, so removed it
> first instead of creating a subsys headfile with no devices.
> They will be added back when new devices added.
>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: Mark Rutland <mark.rutland@xxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
> Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx>
> Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
> Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 75 +++++
> arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 95 +++++++
> arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 124 ++++++++
> arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 29 ++
> arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi | 25 ++
> arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 57 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 311 +--------------------
> 7 files changed, 412 insertions(+), 304 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
> new file mode 100644
> index 0000000..f6f2b94
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@xxxxxxx>
> + */
> +
> +adma_subsys: bus@59000000 {
I'm a bit concerned by that the unit-address is part of the subsystem
definition. If the subsystem is integrated in a SoC on different
address, the while idea will be broken.
Shawn
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x59000000 0x0 0x59000000 0x2000000>;
> +
> + adma_lpcg: clock-controller@59000000 {
> + reg = <0x59000000 0x2000000>;
> + #clock-cells = <1>;
> + };
> +
> + adma_lpuart0: serial@5a060000 {
> + reg = <0x5a060000 0x1000>;
> + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_UART_0>;
> + status = "disabled";
> + };
> +
> + adma_i2c0: i2c@5a800000 {
> + reg = <0x5a800000 0x4000>;
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
> + clock-names = "per";
> + assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_I2C_0>;
> + status = "disabled";
> + };
> +
> + adma_i2c1: i2c@5a810000 {
> + reg = <0x5a810000 0x4000>;
> + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
> + clock-names = "per";
> + assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_I2C_1>;
> + status = "disabled";
> + };
> +
> + adma_i2c2: i2c@5a820000 {
> + reg = <0x5a820000 0x4000>;
> + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
> + clock-names = "per";
> + assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_I2C_2>;
> + status = "disabled";
> + };
> +
> + adma_i2c3: i2c@5a830000 {
> + reg = <0x5a830000 0x4000>;
> + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
> + clock-names = "per";
> + assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_I2C_3>;
> + status = "disabled";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> new file mode 100644
> index 0000000..ac5131d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@xxxxxxx>
> + */
> +
> +conn_subsys: bus@5b000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
> +
> + conn_lpcg: clock-controller@5b200000 {
> + reg = <0x5b200000 0xb0000>;
> + #clock-cells = <1>;
> + };
> +
> + usdhc1: mmc@5b010000 {
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x5b010000 0x10000>;
> + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> + clock-names = "ipg", "per", "ahb";
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> + power-domains = <&pd IMX_SC_R_SDHC_0>;
> + status = "disabled";
> + };
> +
> + usdhc2: mmc@5b020000 {
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x5b020000 0x10000>;
> + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> + clock-names = "ipg", "per", "ahb";
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> + power-domains = <&pd IMX_SC_R_SDHC_1>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + status = "disabled";
> + };
> +
> + usdhc3: mmc@5b030000 {
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x5b030000 0x10000>;
> + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> + clock-names = "ipg", "per", "ahb";
> + assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> + assigned-clock-rates = <200000000>;
> + power-domains = <&pd IMX_SC_R_SDHC_2>;
> + status = "disabled";
> + };
> +
> + fec1: ethernet@5b040000 {
> + reg = <0x5b040000 0x10000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
> + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
> + fsl,num-tx-queues=<3>;
> + fsl,num-rx-queues=<3>;
> + power-domains = <&pd IMX_SC_R_ENET_0>;
> + status = "disabled";
> + };
> +
> + fec2: ethernet@5b050000 {
> + reg = <0x5b050000 0x10000>;
> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
> + <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
> + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
> + fsl,num-tx-queues=<3>;
> + fsl,num-rx-queues=<3>;
> + power-domains = <&pd IMX_SC_R_ENET_1>;
> + status = "disabled";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> new file mode 100644
> index 0000000..1c6ba8d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@xxxxxxx>
> + */
> +
> +lsio_subsys: bus@5d000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
> +
> + lsio_lpcg: clock-controller@5d400000 {
> + reg = <0x5d400000 0x400000>;
> + #clock-cells = <1>;
> + };
> +
> + lsio_mu0: mailbox@5d1b0000 {
> + reg = <0x5d1b0000 0x10000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <0>;
> + status = "disabled";
> + };
> +
> + lsio_mu1: mailbox@5d1c0000 {
> + reg = <0x5d1c0000 0x10000>;
> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + };
> +
> + lsio_mu3: mailbox@5d1e0000 {
> + reg = <0x5d1e0000 0x10000>;
> + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <0>;
> + status = "disabled";
> + };
> +
> + lsio_mu4: mailbox@5d1f0000 {
> + reg = <0x5d1f0000 0x10000>;
> + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <0>;
> + status = "disabled";
> + };
> +
> + lsio_gpio0: gpio@5d080000 {
> + reg = <0x5d080000 0x10000>;
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_0>;
> + };
> +
> + lsio_gpio1: gpio@5d090000 {
> + reg = <0x5d090000 0x10000>;
> + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_1>;
> + };
> +
> + lsio_gpio2: gpio@5d0a0000 {
> + reg = <0x5d0a0000 0x10000>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_2>;
> + };
> +
> + lsio_gpio3: gpio@5d0b0000 {
> + reg = <0x5d0b0000 0x10000>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_3>;
> + };
> +
> + lsio_gpio4: gpio@5d0c0000 {
> + reg = <0x5d0c0000 0x10000>;
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_4>;
> + };
> +
> + lsio_gpio5: gpio@5d0d0000 {
> + reg = <0x5d0d0000 0x10000>;
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_5>;
> + };
> +
> + lsio_gpio6: gpio@5d0e0000 {
> + reg = <0x5d0e0000 0x10000>;
> + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_6>;
> + };
> +
> + lsio_gpio7: gpio@5d0f0000 {
> + reg = <0x5d0f0000 0x10000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + power-domains = <&pd IMX_SC_R_GPIO_7>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
> new file mode 100644
> index 0000000..2486c72
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@xxxxxxx>
> + */
> +
> +&adma_lpcg {
> + compatible = "fsl,imx8qxp-lpcg-adma";
> +};
> +
> +&adma_lpuart0 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +};
> +
> +&adma_i2c0 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +};
> +
> +&adma_i2c1 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +};
> +
> +&adma_i2c2 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +};
> +
> +&adma_i2c3 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
> new file mode 100644
> index 0000000..27a3b46
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@xxxxxxx>
> + */
> +
> +&conn_lpcg {
> + compatible = "fsl,imx8qxp-lpcg-conn";
> +};
> +
> +&usdhc1 {
> + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> +};
> +
> +&usdhc2 {
> + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> +};
> +
> +&fec1 {
> + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
> +};
> +
> +&fec2 {
> + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
> new file mode 100644
> index 0000000..842849b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@xxxxxxx>
> + */
> +
> +&lsio_lpcg {
> + compatible = "fsl,imx8qxp-lpcg-lsio";
> +};
> +
> +&lsio_mu0 {
> + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +};
> +
> +&lsio_mu1 {
> + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +};
> +
> +&lsio_mu3 {
> + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +};
> +
> +&lsio_mu4 {
> + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +};
> +
> +&lsio_gpio0 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio1 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio2 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio3 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio4 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio5 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio6 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> +
> +&lsio_gpio7 {
> + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 4c3dd95..c27043c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -139,308 +139,11 @@
> clock-frequency = <24000000>;
> clock-output-names = "xtal_24MHz";
> };
> -
> - adma_subsys: bus@59000000 {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x59000000 0x0 0x59000000 0x2000000>;
> -
> - adma_lpcg: clock-controller@59000000 {
> - compatible = "fsl,imx8qxp-lpcg-adma";
> - reg = <0x59000000 0x2000000>;
> - #clock-cells = <1>;
> - };
> -
> - adma_lpuart0: serial@5a060000 {
> - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> - reg = <0x5a060000 0x1000>;
> - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
> - clock-names = "ipg";
> - power-domains = <&pd IMX_SC_R_UART_0>;
> - status = "disabled";
> - };
> -
> - adma_i2c0: i2c@5a800000 {
> - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> - reg = <0x5a800000 0x4000>;
> - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
> - clock-names = "per";
> - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
> - assigned-clock-rates = <24000000>;
> - power-domains = <&pd IMX_SC_R_I2C_0>;
> - status = "disabled";
> - };
> -
> - adma_i2c1: i2c@5a810000 {
> - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> - reg = <0x5a810000 0x4000>;
> - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
> - clock-names = "per";
> - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
> - assigned-clock-rates = <24000000>;
> - power-domains = <&pd IMX_SC_R_I2C_1>;
> - status = "disabled";
> - };
> -
> - adma_i2c2: i2c@5a820000 {
> - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> - reg = <0x5a820000 0x4000>;
> - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
> - clock-names = "per";
> - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
> - assigned-clock-rates = <24000000>;
> - power-domains = <&pd IMX_SC_R_I2C_2>;
> - status = "disabled";
> - };
> -
> - adma_i2c3: i2c@5a830000 {
> - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> - reg = <0x5a830000 0x4000>;
> - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-parent = <&gic>;
> - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
> - clock-names = "per";
> - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
> - assigned-clock-rates = <24000000>;
> - power-domains = <&pd IMX_SC_R_I2C_3>;
> - status = "disabled";
> - };
> - };
> -
> - conn_subsys: bus@5b000000 {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
> -
> - conn_lpcg: clock-controller@5b200000 {
> - compatible = "fsl,imx8qxp-lpcg-conn";
> - reg = <0x5b200000 0xb0000>;
> - #clock-cells = <1>;
> - };
> -
> - usdhc1: mmc@5b010000 {
> - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> - interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> - reg = <0x5b010000 0x10000>;
> - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> - clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> - assigned-clock-rates = <200000000>;
> - power-domains = <&pd IMX_SC_R_SDHC_0>;
> - status = "disabled";
> - };
> -
> - usdhc2: mmc@5b020000 {
> - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> - interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
> - reg = <0x5b020000 0x10000>;
> - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> - clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> - assigned-clock-rates = <200000000>;
> - power-domains = <&pd IMX_SC_R_SDHC_1>;
> - fsl,tuning-start-tap = <20>;
> - fsl,tuning-step= <2>;
> - status = "disabled";
> - };
> -
> - usdhc3: mmc@5b030000 {
> - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
> - interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
> - reg = <0x5b030000 0x10000>;
> - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> - clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> - assigned-clock-rates = <200000000>;
> - power-domains = <&pd IMX_SC_R_SDHC_2>;
> - status = "disabled";
> - };
> -
> - fec1: ethernet@5b040000 {
> - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
> - reg = <0x5b040000 0x10000>;
> - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
> - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
> - fsl,num-tx-queues=<3>;
> - fsl,num-rx-queues=<3>;
> - power-domains = <&pd IMX_SC_R_ENET_0>;
> - status = "disabled";
> - };
> -
> - fec2: ethernet@5b050000 {
> - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
> - reg = <0x5b050000 0x10000>;
> - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
> - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
> - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
> - fsl,num-tx-queues=<3>;
> - fsl,num-rx-queues=<3>;
> - power-domains = <&pd IMX_SC_R_ENET_1>;
> - status = "disabled";
> - };
> - };
> -
> - lsio_subsys: bus@5d000000 {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
> -
> - lsio_lpcg: clock-controller@5d400000 {
> - compatible = "fsl,imx8qxp-lpcg-lsio";
> - reg = <0x5d400000 0x400000>;
> - #clock-cells = <1>;
> - };
> -
> - lsio_mu0: mailbox@5d1b0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> - reg = <0x5d1b0000 0x10000>;
> - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> - #mbox-cells = <0>;
> - status = "disabled";
> - };
> -
> - lsio_mu1: mailbox@5d1c0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> - reg = <0x5d1c0000 0x10000>;
> - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
> - #mbox-cells = <2>;
> - };
> -
> - lsio_mu3: mailbox@5d1e0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> - reg = <0x5d1e0000 0x10000>;
> - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
> - #mbox-cells = <0>;
> - status = "disabled";
> - };
> -
> - lsio_mu4: mailbox@5d1f0000 {
> - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> - reg = <0x5d1f0000 0x10000>;
> - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
> - #mbox-cells = <0>;
> - status = "disabled";
> - };
> -
> - lsio_gpio0: gpio@5d080000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d080000 0x10000>;
> - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_0>;
> - };
> -
> - lsio_gpio1: gpio@5d090000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d090000 0x10000>;
> - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_1>;
> - };
> -
> - lsio_gpio2: gpio@5d0a0000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d0a0000 0x10000>;
> - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_2>;
> - };
> -
> - lsio_gpio3: gpio@5d0b0000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d0b0000 0x10000>;
> - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_3>;
> - };
> -
> - lsio_gpio4: gpio@5d0c0000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d0c0000 0x10000>;
> - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_4>;
> - };
> -
> - lsio_gpio5: gpio@5d0d0000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d0d0000 0x10000>;
> - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_5>;
> - };
> -
> - lsio_gpio6: gpio@5d0e0000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d0e0000 0x10000>;
> - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_6>;
> - };
> -
> - lsio_gpio7: gpio@5d0f0000 {
> - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
> - reg = <0x5d0f0000 0x10000>;
> - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - power-domains = <&pd IMX_SC_R_GPIO_7>;
> - };
> - };
> + #include "imx8-ss-adma.dtsi"
> + #include "imx8-ss-conn.dtsi"
> + #include "imx8-ss-lsio.dtsi"
> };
> +
> +#include "imx8qxp-ss-adma.dtsi"
> +#include "imx8qxp-ss-conn.dtsi"
> +#include "imx8qxp-ss-lsio.dtsi"
> --
> 2.7.4
>
>
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