On Wed, Mar 27, 2019 at 09:20:00AM +0100, Guido Günther wrote:
> Add support for the MIXEL DPHY IP as found in the NXP's i.MX8MQ.
>
> Signed-off-by: Guido Günther <agx@xxxxxxxxxxx>
> Reviewed-by: Sam Ravnborg <sam@xxxxxxxxxxxx>
> ---
> .../bindings/phy/mixel,mipi-dsi-phy.txt | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> new file mode 100644
> index 000000000000..d3646580412a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> @@ -0,0 +1,29 @@
> +Mixel DSI PHY for i.MX8
> +
> +The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
> +MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
> +electrical signals for DSI.
> +
> +Required properties:
> +- compatible: Must be:
> + - "mixel,imx8mq-mipi-dphy"
If you had a fallback for mixel, then it would make sense, but as this
is imx8mq specifc 'fsl' should be the vendor prefix.
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Must contain the following entries:
> + - "phy_ref": phandle and specifier referring to the DPHY ref clock
> +- reg: the register range of the PHY controller
> +- #phy-cells: number of cells in PHY, as defined in
> + Documentation/devicetree/bindings/phy/phy-bindings.txt
> + this must be <0>
> +
> +Optional properties:
> +- power-domains: phandle to power domain
> +
> +Example:
> + mipi_dphy: mipi_dphy@30A0030 {
mipi-dphy@... or just dphy@...
> + compatible = "mixel,imx8mq-mipi-dphy";
> + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
> + clock-names = "phy_ref";
> + reg = <0x30A00300 0x100>;
> + power-domains = <&pd_mipi0>;
> + #phy-cells = <0>;
> + };
> --
> 2.20.1
>
