Add nodes to enable DDR devfreq driver on SDM845 SoC.
Signed-off-by: Sibi Sankar <sibis@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 80 ++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 072563f6b6cb..21a0068855e8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -488,6 +489,85 @@
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpubw: cpu-icbw {
+ compatible = "devfreq-icbw";
+ interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>;
+ operating-points-v2 = <&bw_opp_table>;
+ };
+
+ bw_opp_table: bw-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200 {
+ opp-hz = /bits/ 64 < 200000000 >; /* 200 MHz */
+ required-opps = <&cpu0_opp1>;
+ /* 0 MB/s average and 762 MB/s peak bandwidth */
+ opp-bw-MBs = <0 762>;
+ };
+
+ opp-300 {
+ opp-hz = /bits/ 64 < 300000000 >; /* 300 MHz */
+ /* 0 MB/s average and 1144 MB/s peak bandwidth */
+ opp-bw-MBs = <0 1144>;
+ };
+
+ opp-451 {
+ opp-hz = /bits/ 64 < 451000000 >; /* 451 MHz */
+ /* 0 MB/s average and 1720 MB/s peak bandwidth */
+ opp-bw-MBs = <0 1720>;
+ required-opps = <&cpu0_opp6>;
+ };
+
+ opp-547 {
+ opp-hz = /bits/ 64 < 547000000 >; /* 547 MHz */
+ /* 0 MB/s average and 2086 MB/s peak bandwidth */
+ opp-bw-MBs = <0 2086>;
+ required-opps = <&cpu0_opp11>;
+ };
+
+ opp-681 {
+ opp-hz = /bits/ 64 < 681000000 >; /* 681 MHz */
+ /* 0 MB/s average and 2597 MB/s peak bandwidth */
+ opp-bw-MBs = <0 2597>;
+ required-opps = <&cpu0_opp15>;
+ };
+
+ opp-768 {
+ opp-hz = /bits/ 64 < 768000000 >; /* 768 MHz */
+ /* 0 MB/s average and 2929 MB/s peak bandwidth */
+ opp-bw-MBs = <0 2929>;
+ required-opps = <&cpu4_opp4>;
+ };
+
+ opp-1017 {
+ opp-hz = /bits/ 64 < 1017000000 >; /* 1017 MHz */
+ /* 0 MB/s average and 3879 MB/s peak bandwidth */
+ opp-bw-MBs = <0 3879>;
+ required-opps = <&cpu0_opp16>, <&cpu4_opp5>;
+ };
+
+ opp-1296 {
+ opp-hz = /bits/ 64 < 1296000000 >; /* 1296 MHz */
+ /* 0 MB/s average and 4943 MB/s peak bandwidth */
+ opp-bw-MBs = <0 4943>;
+ required-opps = <&cpu4_opp10>;
+ };
+
+ opp-1555 {
+ opp-hz = /bits/ 64 < 1555000000 >; /* 1555 MHz */
+ /* 0 MB/s average and 5931 MB/s peak bandwidth */
+ opp-bw-MBs = <0 5931>;
+ required-opps = <&cpu4_opp12>;
+ };
+
+ opp-1804 {
+ opp-hz = /bits/ 64 < 1804000000 >; /* 1804 MHz */
+ /* 0 MB/s average and 6881 MB/s peak bandwidth */
+ opp-bw-MBs = <0 6881>;
+ required-opps = <&cpu4_opp15>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
--
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