On Thu, Mar 21, 2019 at 5:30 PM Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote: > > Hi, > > The rest of the series is > Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxx> > > On Thu, Mar 21, 2019 at 04:48:44PM +0800, Chen-Yu Tsai wrote: > > From: Chen-Yu Tsai <wens@xxxxxxxx> > > > > The AXP PMICs allow the user to disable current limiting on the VBUS > > input. While read-out of this setting was already supported by the > > driver, it did not allow the user to configure the PMIC to disable > > current limiting. > > > > Add support for this. > > > > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> > > Do we really want to do that though? That could have some pretty bad > consequences. If I understand the manual correctly, the PMIC has two mode of operation with regards to VBUS. Normal operation means the PMIC will try to limit the current draw to maintain VBUS above the set V_hold (defaults to 4.4V). This is in addition to the current limit set in this patch. The other mode of operation is bypass, where it ignores the voltage limit. Not sure if it also ignores the current limit, but probably not. In any case we don't support this mode in the driver. So I can think of a few cases where this might be bad: 1. High current draw results in excessive voltage drop and heating over line / traces due to insufficient conductor area. This should be covered by the voltage holding mechanism. 2. Over taxing the external power supply. This should also result in some voltage drop for simple power bricks. Advanced ones would either have current limiting or over-current protection. What bad consequences are you thinking of? ChenYu
