Hello Simon,
Thank you for your feedback!
> From: Simon Horman <horms@xxxxxxxxxxxx>
> Sent: 22 March 2019 10:47
> Subject: Re: [PATCH 1/2] ARM: dts: r8a77470: Add DU support
>
> On Tue, Mar 19, 2019 at 12:21:38PM +0000, Fabrizio Castro wrote:
> > This commit adds DU support to the RZ/G1C (a.k.a. r8a77470)
> > specific device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@xxxxxxxxxxxxxx>
> > ---
> > arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > index f4e232b..493cf2b 100644
> > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > @@ -643,6 +643,38 @@
> > resets = <&cpg 408>;
> > };
> >
> > + du: display@feb00000 {
> > + compatible = "renesas,du-r8a77470";
> > + reg = <0 0xfeb00000 0 0x40000>;
> > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 724>,
> > + <&cpg CPG_MOD 723>;
>
> I do not see MSTP 7 bit 23 documented as used by DU
> in the User's Manual: Hardware v1.00 Oct 13, 2017.
>
> Do you have more recent documentation or some insight in this area?
I have the same document, and I can see the bit defined in page 7A-16.
Perhaps you checked the Software Reset Register?
Thanks,
Fab
>
> > + clock-names = "du.0", "du.1";
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + du_out_rgb0: endpoint {
> > + };
> > + };
> > + port@1 {
> > + reg = <1>;
> > + du_out_rgb1: endpoint {
> > + };
> > + };
> > + port@2 {
> > + reg = <2>;
> > + du_out_lvds0: endpoint {
> > + };
> > + };
> > + };
> > + };
> > +
> > prr: chipid@ff000044 {
> > compatible = "renesas,prr";
> > reg = <0 0xff000044 0 4>;
> > --
> > 2.7.4
> >
