RE: [PATCH v2 3/3] arm64: dts: imx: Add i.mx8mm evk basic dts support

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> Subject: Re: [PATCH v2 3/3] arm64: dts: imx: Add i.mx8mm evk basic dts
....

> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> > @@ -0,0 +1,238 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mm.dtsi"
> > +
> > +/ {
> > +	model = "FSL i.MX8MM EVK board";
> > +	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> 
> The board compatible should be added to
> Documentation/devicetree/bindings/arm/fsl.yaml as well.

Thanks, I will it.

> > +
> > +	chosen {
> > +		bootargs = "console=ttymxc1,115200
> > +earlycon=ec_imx6q,0x30890000,115200";
> 
> Is it really necessary to have a bootargs in DT?
> 

It is not very necessary, I will remove it.

> > +		stdout-path = &uart2;
> > +	};
> > +
> > +	leds {
> > +		compatible = "gpio-leds";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_gpio_led>;
> > +
> > +		status {
> > +			label = "status";
> > +			gpios = <&gpio3 16 0>;
> 
> Use GPIO_ACTIVE_HIGH.
> 

OK, thanks

> > +			default-state = "on";
> > +		};
> > +	};
> > +
> > +	reg_usdhc2_vmmc: regulator-usdhc2 {
> > +		compatible = "regulator-fixed";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> > +		regulator-name = "VSD_3V3";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > +		off-on-delay = <20000>;
> 
> Unsupported property?
> 

Yes, I will remove it

BR
Jacky

> Shawn
> 
> > +		enable-active-high;
> > +	};
> > +};
> > +
> > +&fec1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_fec1>;
> > +	phy-mode = "rgmii-id";
> > +	phy-handle = <&ethphy0>;
> > +	fsl,magic-packet;
> > +	status = "okay";
> > +
> > +	mdio {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		ethphy0: ethernet-phy@0 {
> > +			compatible = "ethernet-phy-ieee802.3-c22";
> > +			reg = <0>;
> > +			at803x,led-act-blind-workaround;
> > +			at803x,eee-okay;
> > +			at803x,vddio-1p8v;
> > +		};
> > +	};
> > +};
> > +
> > +&uart2 { /* console */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart2>;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> > +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> > +	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> > +	bus-width = <4>;
> > +	vmmc-supply = <&reg_usdhc2_vmmc>;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc3 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc3>;
> > +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > +	bus-width = <8>;
> > +	non-removable;
> > +	status = "okay";
> > +};
> > +
> > +&wdog1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_wdog>;
> > +	fsl,ext-reset-output;
> > +	status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +	pinctrl-names = "default";
> > +
> > +	pinctrl_fec1: fec1grp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
> > +			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
> > +			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
> > +			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
> > +			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
> > +			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
> > +			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
> > +			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
> > +			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
> > +			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
> > +			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
> > +			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
> > +			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> 	0x91
> > +			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 	0x1f
> > +			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
> > +		>;
> > +	};
> > +
> > +	pinctrl_gpio_led: gpioledgrp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
> > +		>;
> > +	};
> > +
> > +	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart2: uart2grp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
> > +			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc2_gpio: usdhc2grpgpio {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc2: usdhc2grp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
> > +			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
> > +			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
> > +			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
> > +			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
> > +			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
> > +			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
> > +			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
> > +			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
> > +			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
> > +			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
> > +			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
> > +			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
> > +			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
> > +			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
> > +			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
> > +			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
> > +			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
> > +			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3: usdhc3grp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
> > +			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 	0x1d0
> > +			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 	0x190
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
> > +			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 	0x1d4
> > +			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 	0x194
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
> > +			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
> 	0x1d6
> > +			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> 	0x196
> > +		>;
> > +	};
> > +
> > +	pinctrl_wdog: wdoggrp {
> > +		fsl,pins = <
> > +			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
> > +		>;
> > +	};
> > +};
> > +
> > --
> > 1.9.1
> >
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