Hi, Rob Best Regards! Anson Huang > -----Original Message----- > From: Rob Herring [mailto:robh@xxxxxxxxxx] > Sent: 2019年3月12日 6:53 > To: Anson Huang <anson.huang@xxxxxxx> > Cc: mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; > s.hauer@xxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx> > Subject: Re: [PATCH V4 1/3] dt-bindings: memory-controllers: freescale: add > MMDC binding doc > > On Fri, Mar 01, 2019 at 01:24:18AM +0000, Anson Huang wrote: > > Freescale MMDC (Multi Mode DDR Controller) driver is supported since > > i.MX6Q, but not yet documented, this patch adds binding doc for MMDC > > module driver. > > > > Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx> > > --- > > Changes since V3: > > - add i.MX6QP compatible name. > > --- > > .../bindings/memory-controllers/fsl/mmdc.txt | 33 > ++++++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt > > > > diff --git > > a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt > > b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt > > new file mode 100644 > > index 0000000..e4e0b50 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory- > controllers/fsl/mmdc.tx > > +++ t > > @@ -0,0 +1,33 @@ > > +Freescale Multi Mode DDR controller (MMDC) > > + > > +Required properties : > > +- compatible : should be one of following: > > + for i.MX6Q/i.MX6DL: > > + - "fsl,imx6q-mmdc"; > > + for i.MX6QP: > > + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; > > + for i.MX6SL: > > + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; > > + for i.MX6SLL: > > + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; > > + for i.MX6SX: > > + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; > > + for i.MX6UL/i.MX6ULL/i.MX6ULZ: > > + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; > > + for i.MX7ULP: > > + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; > > +- reg : address and size of MMDC DDR controller registers > > + > > +Optional properties : > > +- clocks : the clock provided by the SoC to access the MMDC registers > > + > > +Example : > > + mmdc0: memory-controller@21b0000 { /* MMDC0 */ > > + compatible = "fsl,imx6q-mmdc"; > > + reg = <0x021b0000 0x4000>; > > + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; > > + } > > + > > + mmdc1: memory-controller@21b4000 { /* MMDC1 */ > > + reg = <0x021b4000 0x4000>; > > What is this node? No compatible here should be considered invalid. > > Seems like maybe the 1st node should have 2 register ranges if you want a > single device. I think mmdc1's compatible is missed from beginning, I will add a separate patch for it and make its status as disabled by default, since most of i.MX6 platforms ONLY uses mmdc0, ONLY very few special platforms use dual channels. Thanks, Anson. > > Rob
