On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote: > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical > MIPI clock topology in Allwinner DSI controller. > > TCON dotclock driver is computing the desired DCLK divider based on > panel pixel clock along with input DCLK min, max divider values from > tcon driver and that would eventually set the pll-mipi clock rate. > > The current code allows the TCON clock divider to have a default 4 > for min, max ranges that would fail to compute the desired pll-mipi > rate while supporting new panels. > > So, add the computation logic 'format/lanes' to dclk min and max dividers > and instead of default 4. This computation logic align with Allwinner A64 > BSP, hoping that would work even for A33. Last time we discussed this, we found out that this wasn't the case, even in the BSP. What compelling evidence have you found that makes you say otherwise? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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