On 06/03/2019 10:21, Miquel Raynal wrote: > The CP110 SATA unit has 2 ports, and a dedicated ICU entry per > port. In the past, the AHCI SATA driver only supported one interrupt > per SATA unit. To solve this conflict, the 2 SATA wired interrupts in > the South-Bridge got configured as 1 GIC interrupt in the > North-Bridge, regardless of the number of SATA ports actually > enabled/in use, and the bindings only referenced the interrupt of one > port. > > Since then, this limitation has been addressed and this patch ensures > backward compatibility with old DTs not describing SATA ports > correctly directly from the AHCI MVEBU driver. This way, we will be > able to drop the hack from the ICU driver. IOW, when the A8k > compatible string is used and there is no sub-nodes in the DT, we > fake the creation and mapping of the second (missing) interrupt. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> It'd be good to add that all these hacks only exist for the purpose of DT. The same HW booting with ACPI doesn't require any of this because the firmware abstracts stuff that the kernel shouldn't be concerned with the first place. Thanks, M. -- Jazz is not dead. It just smells funny...
