On 03/01/19 22:29, Samuel Holland wrote:
> The H3 and H5 SoCs contain a message box that can be used to send
> messages and interrupts back and forth between the ARM application CPUs
> and the ARISC coprocessor. Add a device tree node for it.
>
> Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index a4c757c0b741..a42fd3f9739e 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -227,6 +227,16 @@
> #size-cells = <0>;
> };
>
> + msgbox: mailbox@1c17000 {
> + compatible = "allwinner,sun8i-h3-msgbox",
> + "allwinner,sun6i-a31-msgbox";
> + reg = <0x01c17000 0x1000>;
> + clocks = <&ccu CLK_BUS_MSGBOX>;
> + resets = <&ccu RST_BUS_MSGBOX>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
This should be 1. And it was caught by the new DTB schema validation :)
> + };
> +
> usb_otg: usb@1c19000 {
> compatible = "allwinner,sun8i-h3-musb";
> reg = <0x01c19000 0x400>;
>
