Quoting Abel Vesa (2019-03-05 01:49:16) > IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. > All the following clock ids are now decreased by 10 to keep the numbering > right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with > IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and > all the following ids are updated accordingly. Why do the numbers need to be consecutive? This looks difficult to merge given that the commit that's being "fixed" is in v5.0 and thus the integer value of these defines is pretty much an ABI. So if there are holes in the space, I suggest we leave them there unless something is really wrong or unworkable with that solution. BTW, it would be great if the binding header was generated once and then never changed again so that we don't have to spend time on these sorts of patches in the future. Please try to fully describe each possible clk that might be used with a particular binding instead of adding new clk ids over time, especially if you have access to the silicon manufacturer documentation and can easily figure out all the clks that are there beforehand.
