On 5/03/19 1:57 PM, Andrew Lunn wrote: > On Tue, Mar 05, 2019 at 11:51:52AM +1300, Chris Packham wrote: >> The orion watchdog can either reset the CPU or generate an interrupt. >> The interrupt would be useful for debugging as it provides panic() >> output about the watchdog expiry, however if the interrupt is used the >> watchdog can't reset the CPU in the event of being stuck in a loop with >> interrupts disabled or if the CPU is prevented from accessing memory >> (e.g. an unterminated DMA). >> >> All of the orion based CPU cores (at least back as far as Kirkwood) have >> spare timers that aren't currently used by the Linux kernel. Actually this appears to be incorrect Kirkwood does configure timer1 as a clockevent timer. So I can't just grab timer1 for all platforms. >> We can use >> timer1 to provide a pre-timeout ahead of the watchdog timer and provide >> the possibility of gathering debug before the reset triggers. > > Hi Chris > > I had a quick look at other drivers implementing pre-timeout. They > seem to call watchdog_notify_pretimeout(). I don't see that here? What > happens when timer1 fires? > It invokes the regular orion_wdt_irq(). On Armada-385 prior to this change the irq was not specified because the reset always kicked in so there was no point. For correctness I could make the devicetree binding specify 2 interrupts. One for the regular watchdog interrupt (which would never usually get hit because the reset would kick in) and one for the pretimeout/timer1. >> @@ -169,38 +174,46 @@ static int armadaxp_wdt_clock_init(struct platform_device *pdev, >> } >> >> /* Enable the fixed watchdog clock input */ >> - atomic_io_modify(dev->reg + TIMER_CTRL, >> - WDT_AXP_FIXED_ENABLE_BIT, >> - WDT_AXP_FIXED_ENABLE_BIT); >> + val = WDT_AXP_FIXED_ENABLE_BIT | TIMER1_FIXED_ENABLE_BIT; >> + atomic_io_modify(dev->reg + TIMER_CTRL, val, val); >> >> dev->clk_rate = clk_get_rate(dev->clk); >> + >> + > > One blank line is sufficient, > > >> return 0; >> } > > Andrew >
