Hello! On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon <bbrezillon@xxxxxxxxxx>) wrote: > HyperFlash devices are compliant with CFI AMD/Fujitsu Extended Command > Set(0x0002) for flash operations, therefore drivers/mtd/chips/cfi_cmdset_0002.c > can be use as is. But these devices do not support DQ polling method of > determining chip ready/good status. These flashes provide Status > Register whose bits can be polled to know status of flash operation. > > Cypress HyperFlash datasheet here[1], talks about CFI Amd/Fujitsu > Extended Query version 1.5. Bit 0 of "Software Features supported" field > of CFI Primary Vendor-Specific Extended Query table indicates > presence/absence of status register and Bit 1 indicates whether or not > DQ polling is supported. Using these bits, its possible to determine > whether flash supports DQ polling or need to use Status Register. > > Add support for polling status register to know device ready/status of > erase/write operations when DQ polling is not supported. > > [1] https://www.cypress.com/file/213346/download > > Signed-off-by: Vignesh R <vigneshr@xxxxxx> > --- > > Note: PRI extended query table size is bigger on 1.5 than on older > revision. Not sure if this causes problems on older rev. because of > reading beyond current size. > > drivers/mtd/chips/cfi_cmdset_0002.c | 50 +++++++++++++++++++++++++++++ > include/linux/mtd/cfi.h | 5 +++ > 2 files changed, 55 insertions(+) > > diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c > index 72428b6bfc47..7a4ef0237750 100644 > --- a/drivers/mtd/chips/cfi_cmdset_0002.c > +++ b/drivers/mtd/chips/cfi_cmdset_0002.c [...] > @@ -97,6 +105,18 @@ static struct mtd_chip_driver cfi_amdstd_chipdrv = { > .module = THIS_MODULE > }; > > +/* > + * Use status register to poll for Erase/write completion when DQ is not > + * supported. This is indicated by Bit[1:0] of SoftwareFeatures field in > + * CFI Primary Vendor-Specific Extended Query table 1.5 > + */ > +static int cfi_use_status_reg(struct cfi_private *cfi) > +{ > + struct cfi_pri_amdstd *extp = cfi->cmdset_priv; > + > + return (extp->MinorVersion >= '5') && > + ((extp->SoftwareFeatures & 0x11) == 1); Parens not necessary here. [...] > @@ -744,8 +764,21 @@ static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) > */ > static int __xipram chip_ready(struct map_info *map, unsigned long addr) > { > + struct cfi_private *cfi = map->fldrv_priv; > map_word d, t; > > + if (cfi_use_status_reg(cfi)) { > + /* > + * For chips that support status register, check device > + * ready bit > + */ > + cfi_send_gen_cmd(0x70, cfi->addr_unlock1, 0, map, cfi, > + cfi->device_type, NULL); > + d = map_read(map, addr); > + > + return (d.x[0] & CFI_SR_DRB); Again, parens not needed. [...] Other than that, looks good. MBR, Sergei
