On Sun, Feb 17, 2019 at 1:09 AM Yong Wu <yong.wu@xxxxxxxxxxxx> wrote: > > There are 2 mmu cells in a M4U HW. we could adjust some larbs entering > mmu0 or mmu1 to balance the bandwidth via the smi-common register > SMI_BUS_SEL(0x220)(Each larb occupy 2 bits). > > In mt8183, For better performance, we switch larb1/2/5/7 to enter > mmu1 while the others still keep enter mmu0. > > In mt8173 and mt2712, we don't get the performance issue, > Keep its default value(0x0), that means all the larbs enter mmu0. > > Note: smi gen1(mt2701/mt7623) don't have this bus_sel. > > And, the base of smi-common is completely different with smi_ao_base > of gen1, thus I add new variable for that. > > CC: Matthias Brugger <matthias.bgg@xxxxxxxxx> > Signed-off-by: Yong Wu <yong.wu@xxxxxxxxxxxx> Reviewed-by: Evan Green <evgreen@xxxxxxxxxxxx>
