On Mon, Feb 18, 2019 at 4:49 PM Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote:
>
> On Sun, Feb 17, 2019 at 11:23:13AM -0500, Yangtao Li wrote:
> > Add support for H5's SID controller.
> >
> > Signed-off-by: Yangtao Li <tiny.windzz@xxxxxxxxx>
> > ---
> > drivers/nvmem/sunxi_sid.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
> > index 570a2e354f30..036029e90921 100644
> > --- a/drivers/nvmem/sunxi_sid.c
> > +++ b/drivers/nvmem/sunxi_sid.c
> > @@ -219,11 +219,17 @@ static const struct sunxi_sid_cfg sun50i_a64_cfg = {
> > .size = 0x100,
> > };
> >
> > +static const struct sunxi_sid_cfg sun50i_h5_cfg = {
> > + .value_offset = 0x200,
> > + .size = 0x100,
> > +};
>
> IIRC, there was an endianness issue on the newer SoCs, with the driver
> converting the data from big endian to little endian, while it's
> actually stored little endian in the SID.
About that, it seems the internals are either little endian or native (same
as the bus). Either way the nvmem the driver currently exposes is wrong.
My idea is to keep the current one with the current name, but have it not
associate itself with the DT node. We then register an extra one, called
"sunxi-sid-native" which uses the native endian. This one will be associated
with the DT node, so the THS driver can consume nvmem cells.
What do you think?
> Have you checked the SID content?
On the A64 and H5, directly dumping the SID registers (not using the H3
read method) shows the contents are little or native endian.
ChenYu
