On Wed, Feb 13, 2019 at 06:12:33PM +0000, Frank Li wrote:
> Added binding doc for imx8qxp ddr performance monitor
>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
As a general thing, please put the DT binding earlier in the series than
the code and/or DTs using it, as per:
Documentation/devicetree/bindings/submitting-patches.txt
> ---
> Change from v2 to v3
> * ddr_pmu0 -> ddr-pmu
>
> .../devicetree/bindings/perf/fsl-imx-ddr.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
>
> diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
> new file mode 100644
> index 0000000..9d55182
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
> @@ -0,0 +1,22 @@
> +* Freescale(NXP) IMX8 DDR performance monitor
> +
> +Required properties:
> +
> +- compatible: (standard compatible string) should be one of:
> + "fsl,imx8-ddr-pmu"
> + "fsl,imx8m-ddr-pmu"
Please remove the "(standard xxx)" bits, they're just noise.
Otherwise, this generally looks OK.
Are the DDR PMU registers part of the DDR controller register block?
Thanks,
Mark.
> +
> +- reg: (standard registers property) physical address and size
> +
> +- interrupts: (standard interrupt property) single interrupt
> + generated by the control block
> +
> +Example:
> +
> + ddr-pmu@5c020000 {
> + compatible = "fsl,imx8-ddr-pmu";
> + reg = <0x0 0x5c020000 0x0 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> --
> 2.5.2
>
