On Mon, Feb 04, 2019 at 04:29:56PM +0100, Marco Felsch wrote:
> From: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
>
> The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
> which needs RX and TX clock skew settings to compensate for differences
> in line length. The skew values are taken from barebox commit
> 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
> is based on patches originally provided by Phytec:
>
> TX_CLK line is approx. 54mm longer than other TX lines which adds
> a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
> have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
> This can be done by setting GTX pad skew value to 11100
> Also add a delay for the RX delay lines, needed for the Duallite
> variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.
>
> Cc: Christian Hemp <c.hemp@xxxxxxxxx>
> Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
Applied, thanks.
