Hi Carlo,
On Wed, Jan 30, 2019 at 7:19 AM Carlo Caione <ccaione@xxxxxxxxxxxx> wrote:
>
> Add a node for the Freescale/NXP QuadSPI controller with a proper
> pinctrl set and enable it for the i.MX8MQ EVK board.
> Extend also the AIPS3 memory range to accommodate the QuadSPI-memory
> region.
>
> Signed-off-by: Carlo Caione <ccaione@xxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 27 ++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 16 +++++++++++-
Please split this in two patches: one for the imx8mq.dtsi and other
for the board dts.
> +&spi0 {
I have recently sent a patch adding eCSPI support. Please call this
qspi0 to avoid confusion with the eCSPI name instances.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi>;
> + status = "okay";
> +
> + flash0: n25q256a@0 {
Node names should be generic and label names specific, so:
n25q256a: flash@0
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "micron,n25q256a", "jedec,spi-nor";
> + spi-max-frequency = <29000000>;
> + spi-nor,ddr-quad-read-dummy = <6>;
This property does not exist in mainline.
>
> + spi0: spi@30bb0000 {
qspi0: spi@30bb0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
Please send a separate patch documenting fsl,imx8mq-qspi
