On 1/11/19 6:34 AM, Miquel Raynal wrote: > Hi Jens, > > Jens Axboe <axboe@xxxxxxxxx> wrote on Tue, 4 Dec 2018 17:11:18 -0700: > >> On 12/4/18 12:28 PM, Miquel Raynal wrote: >>> Hello, >>> >>> As part of an effort to bring suspend to RAM support to Armada 3700 >>> SoCs (main target: ESPRESSObin), this series handles the work around >>> the SATA IP. >>> >>> First, a change in the libahci platform adds support for the new PHY >>> framework by following the phy_set_mode()/phy_power_on() >>> sequence. Then, the AHCI MVEBU driver is a bit updated (patch 2 & 3) >>> and a missing initialization is added for the A3700 in patch 4 (only >>> done by the Bootloader before). Missing clock support is implemented >>> in patch 5 to be sure the clock will be resumed before this driver >>> (see [1] for the series adding device links to the clock core). >>> >>> Finally, device trees are updated to reflect the hardware: the missing >>> PHY is added to the ESPRESSObin DT, and the clock is added to the SoC >>> DT (patch 6 & 7). Bindings already document the clock and the PHY so >>> no update is needed on this regard. >> >> Probably the best/easiest to queue this through the libata tree for >> 4.21. Agree? >> > > It looks like this patchset got left aside for 5.0, shall I re-send? (I > rebased on top of 5.0 and the series applied fine). I never got a reply to the above, so I didn't add it. I've now picked up 1-5, 6-7 should go in through someone elses tree. -- Jens Axboe
