Hi, On 1/9/19 05:08, Henry Chen wrote: > On Mon, 2019-01-07 at 18:34 +0200, Georgi Djakov wrote: >> Hi Henry, >> >> On 1/7/19 13:04, Henry Chen wrote: >>> On Thu, 2019-01-03 at 14:53 -0800, Stephen Boyd wrote: >>>> Quoting Henry Chen (2019-01-02 06:09:51) >>>>> The patchsets add support for MediaTek hardware module named DVFSRC >>>>> (dynamic voltage and frequency scaling resource collector). The DVFSRC is >>>>> a HW module which is used to collect all the requests from both software >>>>> and hardware and turn into the decision of minimum operating voltage and >>>>> minimum DRAM frequency to fulfill those requests. >>>>> >>>>> So, This series is to implement the dvfsrc driver to collect all the >>>>> requests of operating voltage or DRAM bandwidth from other device drivers >>>>> likes GPU/Camera through 2 frameworks basically: >>>>> >>>>> 1. PM_QOS_MEMORY_BANDWIDTH from PM QOS: to aggregate the bandwidth >>>>> requirements from different clients >>>> >>>> Have you looked at using the interconnect framework for this instead of >>>> using PM_QOS_MEMORY_BANDWIDTH? Qcom is pushing an interconnect framework >>>> to do DRAM bandwidth requirement aggregation. >>> >>> Sorry, I haven't heard that before. Do you mean is following series >>> patch? >>> https://patchwork.kernel.org/project/linux-arm-msm/list/?series=53775 >>> >> >> Yes, this one. The idea is that consumer drivers like GPU, camera, video >> encoder etc. report their bandwidth needs by using the interconnect API. >> The framework does the aggregation and configures the hardware. In order >> to use it you need to implement a platform-specific dvfsrc interconnect >> provider driver that understands the SoC topology and knows how to >> configure the hardware. I am not familiar with DVFSRC, but it seems to >> me that it can fit as interconnect provider. >> Does this HW module support any QoS priority/latency configuration or is >> it only bandwidth and voltage? >> >> Thanks, >> Georgi > > Hi Georgi, > > Yes, the design is only to support bandwidth and voltage. The one of the > function is to collect the memory bandwidth requirement from consumer > and select the minimum DRAM frequency to fulfill system performance.It > just get the total bandwidth then set it to HW, not involves complex SoC > topology. So we choose to use PM QOS to model that DVFSRC driver can > receive the bandwidth information from consumer driver via > PM_QOS_MEMORY_BANDWIDTH. Ok, good. The current patchset supports bandwidth, but there was a discussion about adding support for latency and priority in the future. Thanks for the information! > Do you have a patch that show how consumer driver used interconnect to > update their requirement. Here are some examples: https://lkml.org/lkml/2018/12/7/584 https://lkml.org/lkml/2018/10/11/499 https://lkml.org/lkml/2018/9/20/986 https://lkml.org/lkml/2018/11/22/772 Thanks, Georgi
