This patch series adds support for L2 internal asynchronous error detection caused by L2 RAM double-bit ECC error or illegal writes to the Interrupt Controller memory-map region on the Cortex A15. Testing: - works as module (loadable & unloadable) - OK - works as build in kernel driver - OK - interrupt registration - OK - appears in EDAC subsystem/sysfs - OK Wladislav Wiebe (2): dt-bindings: edac: ARM Cortex A15 L2 asynchronous error detection EDAC: add ARM Cortex A15 L2 internal asynchronous error detection driver .../bindings/edac/cortex_a15_l2_async_edac.txt | 22 ++++ MAINTAINERS | 8 ++ drivers/edac/Kconfig | 11 ++ drivers/edac/Makefile | 1 + drivers/edac/cortex_a15_l2_async_edac.c | 134 +++++++++++++++++++++ 5 files changed, 176 insertions(+) create mode 100644 .../bindings/edac/cortex_a15_l2_async_edac.txt create mode 100644 drivers/edac/cortex_a15_l2_async_edac.c -- 2.16.1
