On Wed, 2019-01-02 at 14:23 +0800, Nicolas Boichat wrote: > On Tue, Jan 1, 2019 at 11:58 AM Yong Wu <yong.wu@xxxxxxxxxxxx> wrote: > > > > The protect memory setting is a little different in the different SoCs. > > In the register REG_MMU_CTRL_REG(0x110), the TF_PROT(translation fault > > protect) shift bit is normally 4 while it shift 5 bits only in the > > mt8173. This patch delete the complex MACRO and use a common if-else > > instead. > > > > Also, use "F_MMU_TF_PROT_TO_PROGRAM_ADDR" instead of the hard code(2) > > which means the M4U will output the dirty data to the programmed > > address that we allocated dynamically when translation fault occurs. > > > > Signed-off-by: Yong Wu <yong.wu@xxxxxxxxxxxx> > > --- > > @Nicalos, I don't put it in the plat_data since only the previous mt8173 > > shift 5. As I know, the latest SoC always use the new setting like mt2712 > > and mt8183. Thus, I think it is unnecessary to put it in plat_data and > > let all the latest SoC set it. Hence, I still keep "== mt8173" for this > > like the reg REG_MMU_CTRL_REG. > > Should be ok this way. But maybe one way to avoid hard-coding 4/5 > below is to have 2 macros: > > #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) > #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) > > And still use the if below? Thanks for your quick review. OK for me. I will wait Matthias's review for memory/ part. then send the next version. > > > --- > > drivers/iommu/mtk_iommu.c | 12 +++++------- > > 1 file changed, 5 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index eca1536..35a1263 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -53,11 +53,7 @@ > > > > #define REG_MMU_CTRL_REG 0x110 > > #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) > > -#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \ > > - ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5) > > -/* It's named by F_MMU_TF_PROT_SEL in mt2712. */ > > -#define F_MMU_TF_PROTECT_SEL(prot, data) \ > > - (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data)) > > +#define F_MMU_TF_PROT_TO_PROGRAM_ADDR 2 > > > > #define REG_MMU_IVRP_PADDR 0x114 > > > > @@ -521,9 +517,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > return ret; > > } > > > > - regval = F_MMU_TF_PROTECT_SEL(2, data); > > if (data->plat_data->m4u_plat == M4U_MT8173) > > - regval |= F_MMU_PREFETCH_RT_REPLACE_MOD; > > + regval = F_MMU_PREFETCH_RT_REPLACE_MOD | > > + (F_MMU_TF_PROT_TO_PROGRAM_ADDR << 5); > > + else > > + regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR << 4; > > writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); > > > > regval = F_L2_MULIT_HIT_EN | > > -- > > 1.9.1 > >
