On Wed, Dec 19, 2018 at 10:49:38AM -0800, Jack Pham wrote: > Hi Shawn, Kishon, > > On Wed, Dec 19, 2018 at 09:07:36AM +0800, Shawn Guo wrote: > > On Tue, Dec 18, 2018 at 07:46:13PM +0530, Kishon Vijay Abraham I wrote: > > > > > > > > > On 17/12/18 6:04 AM, Shawn Guo wrote: > > > > On Tue, Dec 04, 2018 at 02:01:07PM +0800, Shawn Guo wrote: > > > >> Hi Kishon, > > > >> > > > >> On Tue, Dec 04, 2018 at 10:38:19AM +0530, Kishon Vijay Abraham I wrote: > > > >>> Hi, > > > >>> > > > >>> On 27/11/18 3:37 PM, Shawn Guo wrote: > > > >>>> It adds Synopsys 28nm Femto High-Speed USB PHY driver support, which > > > >>>> is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. > > > >>> > > > >>> Is this Synopsys PHY specific to Qualcomm or could it be used by other vendors > > > >>> (with just changing tuning parameters)? If it could be used by other vendors > > > >>> then it would make sense to add this PHY driver in synopsys directory. > > > >> > > > >> My knowledge is that this Synopsys PHY is specific to Qualcomm SoCs. > > > >> @Sriharsha, correct me if I'm wrong. > > > > > > > > Kishon, > > > > > > > > Do you have any further comments on the patches? We are close the 4.21 > > > > merge window, and I really hope they can hit mainline with 4.21 release. > > > > Thanks. > > > > > > Aren't we waiting for feedback from Sriharsha? > > > > I think no correction means that I'm right :) > > I'm sorry Sriharsha has not yet responded but I can confirm that this > PHY driver would only be specific to Qualcomm SoCs simply because of our > custom register mapping used to control and initialize it. These are > only defined as as HW signals by the Synopsys IP, which have been > synthesized to map to our own IO register space. So really it can be > treated as just a "Qualcomm USB PHY" with acknowledgement that the core > design is licensed from SNPS. Thanks much for confirming, Jack. Shawn
