Convert the ARM GIC binding document to DT schema format using
json-schema.
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: Jason Cooper <jason@xxxxxxxxxxxxxx>
Cc: Marc Zyngier <marc.zyngier@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Signed-off-by: Rob Herring <robh@xxxxxxxxxx>
---
There's numerous warnings this creates with compatible properties in
regards to having fallback compatible strings. We need to decide either
the binding doc was correct or the dts files are wrong and should be
fixed (or some combination). These are the warnings:
compatible: ['arm,arm1176jzf-devchip-gic', 'arm,arm11mp-gic'] is too long
compatible: ['arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is too long
compatible: ['arm,cortex-a5-gic', 'arm,cortex-a9-gic'] is too long
compatible: ['arm,cortex-a7-gic', 'arm,cortex-a15-gic'] is too long
compatible: ['arm,cortex-a7-gic', 'arm,gic-400'] is too long
compatible: ['arm,gic-400', 'arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is too long
compatible: ['arm,gic-400', 'arm,cortex-a15-gic'] is too long
compatible: ['arm,gic-400', 'arm,cortex-a7-gic', 'arm,cortex-a15-gic'] is too long
compatible: ['arm,gic-400', 'arm,cortex-a7-gic'] is too long
compatible: ['brcm,brahma-b15-gic', 'arm,cortex-a15-gic'] is too long
Any suggestions on additional constraints would be helpful. For example,
'cpu_offset' must be a multiple of ? 4KB?
.../bindings/interrupt-controller/arm,gic.txt | 171 ---------------
.../interrupt-controller/arm,gic.yaml | 205 ++++++++++++++++++
2 files changed, 205 insertions(+), 171 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
deleted file mode 100644
index 2f3244648646..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ /dev/null
@@ -1,171 +0,0 @@
-* ARM Generic Interrupt Controller
-
-ARM SMP cores are often associated with a GIC, providing per processor
-interrupts (PPI), shared processor interrupts (SPI) and software
-generated interrupts (SGI).
-
-Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
-Secondary GICs are cascaded into the upward interrupt controller and do not
-have PPIs or SGIs.
-
-Main node required properties:
-
-- compatible : should be one of:
- "arm,arm1176jzf-devchip-gic"
- "arm,arm11mp-gic"
- "arm,cortex-a15-gic"
- "arm,cortex-a7-gic"
- "arm,cortex-a9-gic"
- "arm,eb11mp-gic"
- "arm,gic-400"
- "arm,pl390"
- "arm,tc11mp-gic"
- "brcm,brahma-b15-gic"
- "nvidia,tegra210-agic"
- "qcom,msm-8660-qgic"
- "qcom,msm-qgic2"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The type shall be a <u32> and the value shall be 3.
-
- The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
- interrupts.
-
- The 2nd cell contains the interrupt number for the interrupt type.
- SPI interrupts are in the range [0-987]. PPI interrupts are in the
- range [0-15].
-
- The 3rd cell is the flags, encoded as follows:
- bits[3:0] trigger type and level flags.
- 1 = low-to-high edge triggered
- 2 = high-to-low edge triggered (invalid for SPIs)
- 4 = active high level-sensitive
- 8 = active low level-sensitive (invalid for SPIs).
- bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
- the 8 possible cpus attached to the GIC. A bit set to '1' indicated
- the interrupt is wired to that CPU. Only valid for PPI interrupts.
- Also note that the configurability of PPI interrupts is IMPLEMENTATION
- DEFINED and as such not guaranteed to be present (most SoC available
- in 2014 seem to ignore the setting of this flag and use the hardware
- default value).
-
-- reg : Specifies base physical address(s) and size of the GIC registers. The
- first region is the GIC distributor register base and size. The 2nd region is
- the GIC cpu interface register base and size.
-
-Optional
-- interrupts : Interrupt source of the parent interrupt controller on
- secondary GICs, or VGIC maintenance interrupt on primary GIC (see
- below).
-
-- cpu-offset : per-cpu offset within the distributor and cpu interface
- regions, used when the GIC doesn't have banked registers. The offset is
- cpu-offset * cpu-nr.
-
-- clocks : List of phandle and clock-specific pairs, one for each entry
- in clock-names.
-- clock-names : List of names for the GIC clock input(s). Valid clock names
- depend on the GIC variant:
- "ic_clk" (for "arm,arm11mp-gic")
- "PERIPHCLKEN" (for "arm,cortex-a15-gic")
- "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
- "clk" (for "arm,gic-400" and "nvidia,tegra210")
- "gclk" (for "arm,pl390")
-
-- power-domains : A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle, used when the GIC
- is part of a Power or Clock Domain.
-
-
-Example:
-
- intc: interrupt-controller@fff11000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- interrupt-controller;
- reg = <0xfff11000 0x1000>,
- <0xfff10100 0x100>;
- };
-
-
-* GIC virtualization extensions (VGIC)
-
-For ARM cores that support the virtualization extensions, additional
-properties must be described (they only exist if the GIC is the
-primary interrupt controller).
-
-Required properties:
-
-- reg : Additional regions specifying the base physical address and
- size of the VGIC registers. The first additional region is the GIC
- virtual interface control register base and size. The 2nd additional
- region is the GIC virtual cpu interface register base and size.
-
-- interrupts : VGIC maintenance interrupt.
-
-Example:
-
- interrupt-controller@2c001000 {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x2c001000 0x1000>,
- <0x2c002000 0x2000>,
- <0x2c004000 0x2000>,
- <0x2c006000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
-
-
-* GICv2m extension for MSI/MSI-x support (Optional)
-
-Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
-This is enabled by specifying v2m sub-node(s).
-
-Required properties:
-
-- compatible : The value here should contain "arm,gic-v2m-frame".
-
-- msi-controller : Identifies the node as an MSI controller.
-
-- reg : GICv2m MSI interface register base and size
-
-Optional properties:
-
-- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
- value, this property should contain the SPI base of
- the MSI frame, overriding the HW value.
-
-- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
- value, this property should contain the number of
- SPIs assigned to the frame, overriding the HW value.
-
-Example:
-
- interrupt-controller@e1101000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-controller;
- interrupts = <1 8 0xf04>;
- ranges = <0 0 0 0xe1100000 0 0x100000>;
- reg = <0x0 0xe1110000 0 0x01000>,
- <0x0 0xe112f000 0 0x02000>,
- <0x0 0xe1140000 0 0x10000>,
- <0x0 0xe1160000 0 0x10000>;
- v2m0: v2m@8000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x0 0x80000 0 0x1000>;
- };
-
- ....
-
- v2mN: v2m@9000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x0 0x90000 0 0x1000>;
- };
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
new file mode 100644
index 000000000000..80db566749a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Generic Interrupt Controller v1 and v2
+
+maintainers:
+ - Marc Zyngier <marc.zyngier@xxxxxxx>
+
+description: |+
+ ARM SMP cores are often associated with a GIC, providing per processor
+ interrupts (PPI), shared processor interrupts (SPI) and software
+ generated interrupts (SGI).
+
+ Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
+ Secondary GICs are cascaded into the upward interrupt controller and do not
+ have PPIs or SGIs.
+
+properties:
+ compatible:
+ enum:
+ - arm,arm1176jzf-devchip-gic
+ - arm,arm11mp-gic
+ - arm,cortex-a15-gic
+ - arm,cortex-a7-gic
+ - arm,cortex-a5-gic
+ - arm,cortex-a9-gic
+ - arm,eb11mp-gic
+ - arm,gic-400
+ - arm,pl390
+ - arm,tc11mp-gic
+ - brcm,brahma-b15-gic
+ - nvidia,tegra210-agic
+ - qcom,msm-8660-qgic
+ - qcom,msm-qgic2
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
+ interrupts.
+
+ The 2nd cell contains the interrupt number for the interrupt type.
+ SPI interrupts are in the range [0-987]. PPI interrupts are in the
+ range [0-15].
+
+ The 3rd cell is the flags, encoded as follows:
+ bits[3:0] trigger type and level flags.
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered (invalid for SPIs)
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive (invalid for SPIs).
+ bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
+ the 8 possible cpus attached to the GIC. A bit set to '1' indicated
+ the interrupt is wired to that CPU. Only valid for PPI interrupts.
+ Also note that the configurability of PPI interrupts is IMPLEMENTATION
+ DEFINED and as such not guaranteed to be present (most SoC available
+ in 2014 seem to ignore the setting of this flag and use the hardware
+ default value).
+
+ reg:
+ description: |
+ Specifies base physical address(s) and size of the GIC registers. The
+ first region is the GIC distributor register base and size. The 2nd region
+ is the GIC cpu interface register base and size.
+
+ For GICv2 with virtualization extensions, additional regions are
+ required for specifying the base physical address and size of the VGIC
+ registers. The first additional region is the GIC virtual interface
+ control register base and size. The 2nd additional region is the GIC
+ virtual cpu interface register base and size.
+ minItems: 2
+ maxItems: 4
+
+ interrupts:
+ description: Interrupt source of the parent interrupt controller on
+ secondary GICs, or VGIC maintenance interrupt on primary GIC (see
+ below).
+ maxItems: 1
+
+ cpu-offset:
+ description: per-cpu offset within the distributor and cpu interface
+ regions, used when the GIC doesn't have banked registers. The offset
+ is cpu-offset * cpu-nr.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ description: List of names for the GIC clock input(s). Valid clock names
+ depend on the GIC variant.
+ oneOf:
+ - const: ic_clk # for "arm,arm11mp-gic"
+ - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
+ - items: # for "arm,cortex-a9-gic"
+ - const: PERIPHCLK
+ - const: PERIPHCLKEN
+ - const: clk # for "arm,gic-400" and "nvidia,tegra210"
+ - const: gclk #for "arm,pl390"
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - interrupt-controller
+ - "#interrupt-cells"
+ - reg
+
+patternProperties:
+ "^v2m@[0-9a-f]*$":
+ description: |
+ * GICv2m extension for MSI/MSI-x support (Optional)
+
+ Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
+ This is enabled by specifying v2m sub-node(s).
+
+ properties:
+ compatible:
+ const: arm,gic-v2m-frame
+
+ msi-controller: true
+
+ reg:
+ maxItems: 1
+ description: GICv2m MSI interface register base and size
+
+ arm,msi-base-spi:
+ description: When the MSI_TYPER register contains an incorrect value,
+ this property should contain the SPI base of the MSI frame, overriding
+ the HW value.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ arm,msi-num-spis:
+ description: When the MSI_TYPER register contains an incorrect value,
+ this property should contain the number of SPIs assigned to the
+ frame, overriding the HW value.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - compatible
+ - msi-controller
+ - reg
+
+examples:
+ - |
+ // GICv1
+ intc: interrupt-controller@fff11000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0xfff11000 0x1000>,
+ <0xfff10100 0x100>;
+ };
+
+ - |
+ // GICv2
+ interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c002000 0x2000>,
+ <0x2c004000 0x2000>,
+ <0x2c006000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ - |
+ // GICv2m extension for MSI/MSI-x support
+ interrupt-controller@e1101000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ interrupts = <1 8 0xf04>;
+ ranges = <0 0 0 0xe1100000 0 0x100000>;
+ reg = <0x0 0xe1110000 0 0x01000>,
+ <0x0 0xe112f000 0 0x02000>,
+ <0x0 0xe1140000 0 0x10000>,
+ <0x0 0xe1160000 0 0x10000>;
+
+ v2m0: v2m@8000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0x80000 0 0x1000>;
+ };
+
+ //...
+
+ v2mN: v2m@9000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0x90000 0 0x1000>;
+ };
+ };
+...
--
2.19.1
