Hi Rob, Hi Hanjie, (sorry for being late with my question) On Tue, Dec 18, 2018 at 9:05 AM Hanjie Lin <hanjie.lin@xxxxxxxxxxx> wrote: [...] > +- reg-names: Must be > + - "elbi" External local bus interface registers > + - "cfg" Meson specific registers > + - "phy" Meson PCIE PHY registers I have learned that there are two PHY register designs: - AXG only has a PCIe PHY - G12A has a PHY which supports PCIe and USB 3.0. The PCIe part of this PHY design is compatible with AXG, but this design also supports a USB 3.0 port (it's an exclusive choice: either PCIe *or* USB 3.0) The PCIe controller itself is identical on both, AXG and G12A. This patch adds support for the AXG PCIe controller and PHY within one device-tree node. For G12A I propose to add a separate "phys" property with a phandle to the "combo" PCIe and USB3.0 PHY - this can be part of a separate patch though. I would like to know whether it's OK that for AXG the PCIe PHY is described in the same device-tree node as the PCIe controller (in other words: we're not using a "phys" property here)? Kind Regards Martin
