On Mon, Dec 17, 2018 at 08:32:47AM -0600, Bjorn Helgaas wrote: > On Mon, Dec 17, 2018 at 04:19:39PM +0800, Jianjun Wang wrote: > > On Thu, 2018-12-13 at 08:55 -0600, Bjorn Helgaas wrote: > > > On Thu, Dec 06, 2018 at 09:09:13AM +0800, Jianjun Wang wrote: > > > > The read value of BAR0 is 0xffff_ffff, it's size will be calculated as 4GB > > > > in arm64 but bogus alignment values at arm32, the pcie device and devices > > > > behind this bridge will not be enabled. Fix it's BAR0 resource size to > > > > guarantee the pcie devices will be enabled correctly. > > > > > > So this is a hardware erratum? Per spec, a memory BAR has bit 0 hardwired > > > to 0, and an IO BAR has bit 1 hardwired to 0. > > > > Yes, it only works properly on 64bit platform. > > I don't understand. BARs are supposed to work the same regardless of > whether it's a 32- or 64-bit platform. If this is a workaround for a > hardware defect, please just say that explicitly. I do not understand this either. First thing to do is to describe the problem properly so that we can actually find a solution to it. Lorenzo
