On Mon, 10 Dec 2018 17:15:29 +0000
<Tudor.Ambarus@xxxxxxxxxxxxx> wrote:
> From: Cyrille Pitchen <cyrille.pitchen@xxxxxxxxxxxxx>
>
> This patch configures the QSPI0 controller pin muxing and declares
> a jedec,spi-nor memory.
>
> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> memory which advertises a maximum frequency of 80MHz for Quad IO
> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@xxxxxxxxxxxxx>
> [tudor.ambarus@xxxxxxxxxxxxx:
> - drop partitions,
> - add spi-rx/tx-bus-width
> - change spi-max-frequency to match the 80MHz limit advertised by
> MX25L25673G for Quad IO Fast Read,
> - reword commit message and subject.]
> Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index 518e2b095ccf..171bc82cfbbf 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -108,6 +108,21 @@
> };
>
> apb {
> + qspi0: spi@f0020000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi0_default>;
> + /* status = "okay"; */ /* conflict with sdmmc1 */
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <80000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + m25p,fast-read;
> + };
I'm a bit lost. What's the point of defining this if the QSPI
controller is not enabled?
