Move #clock-cells into the child node and set it to 0 to conform to the
proper binding specification.
Signed-off-by: Evan Green <evgreen@xxxxxxxxxxxx>
Reviewed-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
Tested-by: Vivek Gautam <vivek.gautam@xxxxxxxxxxxxxx>
---
Changes in v2: None
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index b29fe80d72883..44a494c70fa11 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -760,7 +760,6 @@
phy@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x34000 0x488>;
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -783,6 +782,7 @@
reg = <0x035000 0x130>,
<0x035200 0x200>,
<0x035400 0x1dc>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
@@ -796,6 +796,7 @@
reg = <0x036000 0x130>,
<0x036200 0x200>,
<0x036400 0x1dc>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
@@ -809,6 +810,7 @@
reg = <0x037000 0x130>,
<0x037200 0x200>,
<0x037400 0x1dc>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
@@ -822,7 +824,6 @@
phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x7410000 0x1c4>;
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -844,6 +845,7 @@
reg = <0x7410200 0x200>,
<0x7410400 0x130>,
<0x7410600 0x1a8>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
--
2.18.1
