On Fri, 07 Dec 2018 09:20:57 PST (-0800), anup@xxxxxxxxxxxxxx wrote:
On Fri, 7 Dec, 2018, 10:30 PM Palmer Dabbelt <palmer@xxxxxxxxxx wrote:
On Mon, 03 Dec 2018 12:57:31 PST (-0800), atish.patra@xxxxxxx wrote:
> Currently, clocksource registration happens for an invalid cpu
> for non-smp kernels. This lead to kernel panic as cpu hotplug
> registration will fail for those cpus.
>
> Do not proceed if hartid is invalid. Take this opprtunity to
> print appropriate error strings for different failure cases.
>
> Signed-off-by: Atish Patra <atish.patra@xxxxxxx>
> ---
> drivers/clocksource/riscv_timer.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clocksource/riscv_timer.c
b/drivers/clocksource/riscv_timer.c
> index 39de6e49..4af4af47 100644
> --- a/drivers/clocksource/riscv_timer.c
> +++ b/drivers/clocksource/riscv_timer.c
> @@ -108,6 +108,8 @@ static int __init riscv_timer_init_dt(struct
device_node *n)
> int cpuid, hartid, error;
>
> hartid = riscv_of_processor_hartid(n);
> + if (hartid < 0)
> + return hartid;
This seems like it's just hiding a bug somewhere else. We should at least
put
out a WARN here, as I'm not sure the error will propagate anywhere useful.
We need separate DT node for riscv_timer. The riscv_timer is nothing but
SOC timer accessed via rdtime and SBI calls. It can be viewed as one
device. In fact, this is how it's done in ARM/ARM64.
We had that at some point, but this was changed. The logic was that, since the
RISC-V ISA mandates the presence of this timer for all harts, the RISC-V CPU
node is sufficient to encode the presence of a RISC-V timer.
I'm OK changing this, but you should look at the old thread (which I can't
find) to make sure all the arguments are taken into account.
> cpuid = riscv_hartid_to_cpuid(hartid);
>
> if (cpuid != smp_processor_id())
> @@ -115,14 +117,19 @@ static int __init riscv_timer_init_dt(struct
device_node *n)
>
> /* This should be called only for boot cpu */
> riscv_timebase = riscv_timebase_frequency(n);
> - clocksource_register_hz(&riscv_clocksource, riscv_timebase);
> + error = clocksource_register_hz(&riscv_clocksource,
riscv_timebase);
>
> + if (error) {
> + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
> + error, cpuid);
> + return error;
> + }
> error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
> "clockevents/riscv/timer:starting",
> riscv_timer_starting_cpu, riscv_timer_dying_cpu);
> if (error)
> - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
> - error, cpuid);
> + pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
> + error);
> return error;
> }
Regards,
Anup
