On Fri, Dec 7, 2018 at 8:31 AM Paul Walmsley <paul.walmsley@xxxxxxxxxx> wrote: > > > On Fri, 7 Dec 2018, Rob Herring wrote: > > > On Thu, Dec 6, 2018 at 6:46 PM Paul Walmsley <paul.walmsley@xxxxxxxxxx> wrote: > > > On Thu, 6 Dec 2018, Rob Herring wrote: > > > > On Wed, Nov 21, 2018 at 05:06:56PM -0800, Paul Walmsley wrote: > > > > > > > > > .../sifive/sifive-blocks-ip-versioning.txt | 38 +++++++++++++++++++ > > > > > 1 file changed, 38 insertions(+) > > > > > create mode 100644 Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt > > > > > > > > Use the path that was suggested. > > > > > > Could you remind me which one that is? > > > > In this thread: bindings/riscv/sifive/ > > SiFive also produces ARM-based SoCs. Some of those ARM SoCs may use these > IP blocks from sifive-blocks as well. As far as I know, there's nothing > RISC-V-specific about most of these IP blocks. (As an example, there's > nothing CPU architecture-specific about a UART.) Fair enough. As-is is fine. Rob
