Quoting Matthias Kaehlcke (2018-12-04 09:35:49)
> On Tue, Dec 04, 2018 at 08:44:00AM -0800, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2018-11-30 16:52:48)
> > > +
> > > /* custom byte clock divider */
> > > struct clk_bytediv *bytediv;
> > >
> > > @@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> > > DBG("rate=%lu, parent's=%lu", rate, parent_rate);
> > >
> > > temp = rate / 10;
> > > - val = VCO_REF_CLK_RATE / 10;
> > > + if (parent_rate)
> > > + val = parent_rate / 10;
> > > + else
> > > + val = VCO_REF_CLK_DEFAULT_RATE / 10;
> >
> > Is the clk not properly hooked up to a parent sometimes so parent_rate
> > is 0? That sounds odd given the fact that it used to be 'pxo' and that
> > has always existed on the system as 27 MHz. So I'd remove this and just
> > use parent_rate all the time.
>
> I wondered about this, but since I don't have hardware for testing I
> kept the previous hardcoded rate. If we know for sure that 'pxo'
> always exists it should indeed be fine to use the parent rate.
Yes we know for sure. The 'pxo' board clk is there on apq8064 dtsi file
which seems to be the only place this is used. The pxo_board clk is sent
through a 'pxo' clk that's created in drivers/clk/qcom/common.c
qcom_cc_register_board_clk().
