Adds uart2 connections as used on the sbc. This uart is connected via
the soc's pins 3 (TX) and 5 (RX). On the sbc it is pinned out on P4
using pins 31 (RX) and 33 (TX).
Signed-off-by: Hans Ole Hatzel <hohatzel@xxxxxxxx>
Signed-off-by: Julian Scheel <jscheel@xxxxxxxx>
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 16 ++++++++++++++++
arch/arm/boot/dts/imx7d-sbc-imx7.dts | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index e77e0cc7de39..6c2c844dc052 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -214,6 +214,15 @@
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "disabled";
+ fsl;
+};
+
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
@@ -314,6 +323,13 @@
>;
};
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x79
+ MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x79
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
diff --git a/arch/arm/boot/dts/imx7d-sbc-imx7.dts b/arch/arm/boot/dts/imx7d-sbc-imx7.dts
index f8a868552707..74904127fbc6 100644
--- a/arch/arm/boot/dts/imx7d-sbc-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-sbc-imx7.dts
@@ -26,6 +26,10 @@
status = "okay";
};
+&uart2 {
+ status = "okay";
+};
+
&iomuxc {
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
--
2.19.2
