On 2018/12/3 16:02, Andy Shevchenko wrote:
> On Mon, Dec 3, 2018 at 5:48 AM Yu Chen <chenyu56@xxxxxxxxxx> wrote:
>>
>> There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc.
>> 1)SPLIT_BOUNDARY_DISABLE should be set for Host mode
>> 2)A GCTL soft reset should be executed when switch mode
>
>> +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc)
>> +{
>
>> + int reg;
>
> u32? int for register value looks confusing a bit.
Yes, it should be u32.
>
>> + reg = dwc3_readl(dwc->regs, DWC3_GCTL);
>> + reg |= (DWC3_GCTL_CORESOFTRESET);
>> + dwc3_writel(dwc->regs, DWC3_GCTL, reg);
>> +
>> + reg = dwc3_readl(dwc->regs, DWC3_GCTL);
>> + reg &= ~(DWC3_GCTL_CORESOFTRESET);
>> + dwc3_writel(dwc->regs, DWC3_GCTL, reg);
>> +}
>
>> + int reg;
>
> Ditto.
>
