Quoting Aisheng DONG (2018-11-28 23:46:41) > > -----Original Message----- > > From: Stephen Boyd [mailto:sboyd@xxxxxxxxxx] > [...] > > > > > > Changes since v12: > > > * replaced the division in clk_pll_recalc_rate in clk-frac > > > with do_div as suggested by Stephen > > > > > > Abel Vesa (2): > > > clk: imx: Add imx composite clock > > > clk: imx: Add clock driver for i.MX8MQ CCM > > > > > > Lucas Stach (3): > > > dt-bindings: add binding for i.MX8MQ CCM > > > clk: imx: add fractional PLL output clock > > > clk: imx: Add SCCG PLL type > > > > > > > I had to apply this set of fixes to silence sparse and smatch warnings about > > things that are not right. Please take a look over things and see if it's sane. > > > > The change looks good to me and tested ok. > I did not see this patch series in your tree. > Do you want us to apply your changes and re-send for easy pick up? > I applied this version and my fixes. I'll just mark v14 as superseded. Thanks for testing!
