Hello. On 03/13/2014 10:38 PM, Ezequiel Garcia wrote:
From: Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxxxxxxxxxx>
The Armada 38x SoC family has a clock provider called "Core Divider", derived from the fixed 2 GHz main PLL clock. This is similar to the one on A370, A375 and AXP.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxxxxxxxxxx> --- arch/arm/boot/dts/armada-38x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 38fc3a0..76cc27e 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -337,6 +337,14 @@ compatible = "marvell,orion-mdio"; reg = <0x72004 0x4>; }; + + coredivclk: corediv-clock@e4250 {
I would suggest naming the device just "clock@e4250" on the same grounds of having the generic device names.
WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html