On Thu, Nov 01, 2018 at 07:25:23PM -0700, Jeykumar Sankaran wrote:
> DPU is short for the Display Processing Unit. It is the display
> controller on Qualcomm SDM845 chips.
>
> This change adds MDSS and DSI nodes to enable display on the
> target device.
>
> Changes in v2:
> - Beefed up commit message
> - Use SoC specific compatibles for mdss and dpu (Rob H)
> - Use assigned-clocks to set initial clock frequency(Rob H)
> Changes in v3:
> - added IOMMU node
> - Fix device naming (remove _phys)
> - Use correct IRQ_TYPE in interrupt specifiers
>
> Signed-off-by: Jeykumar Sankaran <jsanka@xxxxxxxxxxxxxx>
> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 191 +++++++++++++++++++++++++++++++++++
> 1 file changed, 191 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 0c9a2aa..dd612ac 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -978,6 +978,197 @@
> #thermal-sensor-cells = <1>;
> };
>
> + mdss: mdss@ae00000 {
> + compatible = "qcom,sdm845-mdss";
> + reg = <0xae00000 0x1000>;
> + reg-names = "mdss";
> +
> + power-domains = <&dispcc 0>;
Would the powers-that-be in the power domain prefer this to have a symbolic
value? I see MDSS_GDSC in the bindings header.
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "core";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + assigned-clock-rates = <300000000>;
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x880 0x8>,
> + <&apps_smmu 0xc80 0x8>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mdss_mdp: mdp@ae01000 {
> + compatible = "qcom,sdm845-dpu";
> + reg = <0x0ae01000 0x8f000>,
> + <0x0aeb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "iface", "bus", "core", "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <300000000>,
> + <19200000>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf2_out: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0xae94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>;
> + clock-names = "byte_clk",
> + "byte_intf_clk",
> + "pixel_clk",
> + "core_clk",
> + "iface_clk",
> + "bus_clk";
We will need to remove the _clk extension and fix the code if needed.
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi-phy";
This too, I reckon.
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi0_phy: dsi-phy@ae94400 {
> + compatible = "qcom,dsi-phy-10nm";
> + reg = <0xae94400 0x200>,
> + <0xae94a00 0x1e0>,
> + <0xae94600 0x280>;
I think it would be better if these were in numerical order.
> + reg-names = "dsi_phy",
> + "dsi_pll",
> + "dsi_phy_lane";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "iface_clk";
Remove _clk extension.
> + };
> +
> + dsi1: dsi@ae96000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0xae96000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC1_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>;
> + clock-names = "byte_clk",
> + "byte_intf_clk",
> + "pixel_clk",
> + "core_clk",
> + "iface_clk",
> + "bus_clk";
And here.
> +
> + phys = <&dsi1_phy>;
> + phy-names = "dsi-phy";
And here.
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi1_in: endpoint {
> + remote-endpoint = <&dpu_intf2_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi1_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi1_phy: dsi-phy@ae96400 {
> + compatible = "qcom,dsi-phy-10nm";
> + reg = <0xae96400 0x200>,
> + <0xae96a00 0x10e>,
> + <0xae96600 0x280>;
Numerical order would be preferred.
> + reg-names = "dsi_phy",
> + "dsi_pll",
> + "dsi_phy_lane";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> + clock-names = "iface_clk";
And one more extension.
> + };
> + };
> +
> spmi_bus: spmi@c440000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0xc440000 0x1100>,
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