On Tue, Nov 20, 2018 at 6:53 PM Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote: > > On Mon, Nov 19, 2018 at 04:28:29PM +0530, Jagan Teki wrote: > > On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote: > > > > > > On Fri, Nov 16, 2018 at 10:09:05PM +0530, Jagan Teki wrote: > > > > Loop N1 instruction delay for burst mode lcd panel are > > > > computed as per BSP code. > > > > > > > > Reference code is available in BSP (from linux-sunxi > > > > drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c) > > > > > > > > dsi_dev[sel]->dsi_inst_loop_num.bits.loop_n1= > > > > (panel->lcd_ht-panel->lcd_x)*(150)/(panel->lcd_dclk_freq*8) - 50; > > > > => (((mode->htotal - mode->hdisplay) * 150) / > > > > ((mode->clock / 1000) * 8)) - 50; > > > > > > > > So use the similar computation for loop N1 delay. > > > > > > > > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > > > > > > *why* are you doing this? What is it fixing? on which devices? > > > > You mentioned the separate function to compute the delay for all modes > > [1], ie what I did. did I missing anything? > > You're missing that you are never explaining why that patch is needed > in the first place. Or answering the question I asked a couple of > lines above. OK. The instruction delay varies between video and burst mode. for burst mode panels it is computed based on the panel clock along with horizontal sync+porch timings. Got it, the same I need to update on commit, since you asked about separate delay route I thought you get the proper details.
