On Fri, Nov 02, 2018 at 09:51:49AM +0000, Bhaskar Upadhaya wrote:
>
>
> >-----Original Message-----
> >From: Shawn Guo <shawnguo@xxxxxxxxxx>
> >Sent: Wednesday, October 31, 2018 12:44 PM
> >To: Bhaskar Upadhaya <bhaskar.upadhaya@xxxxxxx>
> >Cc: devicetree@xxxxxxxxxxxxxxx; Harninder Rai <harninder.rai@xxxxxxx>;
> >Sudhanshu Gupta <sudhanshu.gupta@xxxxxxx>; Rajesh Bhagat
> ><rajesh.bhagat@xxxxxxx>; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; Leo Li
> ><leoyang.li@xxxxxxx>
> >Subject: Re: [PATCH v2 1/2] arm64: dts: Add support for NXP LS1028A SoC
> >> + compatible = "fsl,ls1028a";
> >> + interrupt-parent = <&gic>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + cpu0: cpu@0 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a72";
> >> + reg = <0x0>;
> >> + enable-method = "psci";
> >> + clocks = <&clockgen 1 0>;
> >> + next-level-cache = <&l2>;
> >> + cpu-idle-states = <&CPU_PH20>;
> >> + };
> >> +
> >> + cpu1: cpu@1 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a72";
> >> + reg = <0x1>;
> >> + enable-method = "psci";
> >> + clocks = <&clockgen 1 0>;
> >> + next-level-cache = <&l2>;
> >> + cpu-idle-states = <&CPU_PH20>;
> >> + };
> >> +
> >> + l2: l2-cache {
> >> + compatible = "cache";
> >> + };
> >
> >Not sure what's the point of this node without any properties.
>
> Shawn, I looked into the NXP and non-NXP platforms, but all are creating cache nodes with "compatible" being the only property.
Okay, just noticed that the node is referred by next-level-cache
property of cpu node. So I guess this 'dummy' cache node is there only
for architectural integrity/sanity check or something.
Shawn
