Quoting jiada_wang@xxxxxxxxxx (2018-10-25 00:23:47)
> From: Jiada Wang <jiada_wang@xxxxxxxxxx>
>
> Add device tree bindings for avb counter clock for Renesas
> R-Car Socs.
>
> Signed-off-by: Jiada Wang <jiada_wang@xxxxxxxxxx>
> ---
> .../bindings/clock/renesas,avb-clk.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt
> new file mode 100644
> index 000000000000..03bf50b5830c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt
> @@ -0,0 +1,19 @@
> +* Renesas AVB Counter Clock
> +
> +The AVB Counter Clocks are provided by avb_counter8 Clock Generator,
> +avb_counter8 has dividers which operates with S0D1ϕ clock and has
> +8 output clocks.
> +
> +Required Properties:
> + - compatible: Must be "renesas,clk-avb"
> + - reg: Base address and length of the memory resource used by the AVB
> + - #clock-cells: Must be 1
> +
> +Example
> +-------
> +
> + clk_avb: avb-clock@ec5a011c {
> + compatible = "renesas,clk-avb";
> + reg = <0 0xec5a011c 0 0x24>;
This is an odd register offset. Is this just one clk inside of a larger
clk controller?
