On Thu, Oct 18, 2018 at 10:55 AM Laurent Pinchart
<laurent.pinchart@xxxxxxxxxxxxxxxx> wrote:
>
> Hi Icenowy,
>
> Thank you for the patch.
>
> On Thursday, 18 October 2018 10:33:27 EEST Icenowy Zheng wrote:
> > From: Chen-Yu Tsai <wens@xxxxxxxx>
> >
> > The panels shipped with Allwinner devices are very "generic", i.e.
> > they do not have model numbers or reliable sources of information
> > for the timings (that we know of) other than the fex files shipped
> > on them. The dot clock frequency provided in the fex files have all
> > been rounded to the nearest MHz, as that is the unit used in them.
> >
> > We were using the simple panel "urt,umsh-8596md-t" as a substitute
> > for the A13 Q8 tablets in the absence of a specific model for what
> > may be many different but otherwise timing compatible panels. This
> > was usable without any visual artifacts or side effects, until the
> > dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
> > rgb: Validate the clock rate").
> >
> > The reason this check fails is because the dotclock frequency for
> > this model is 33.26 MHz, which is not achievable with our dot clock
> > hardware, and the rate returned by clk_round_rate deviates slightly,
> > causing the driver to reject the display mode.
> >
> > The LCD panels have some tolerance on the dot clock frequency, even
> > if it's not specified in their datasheets.
> >
> > This patch adds a 5% tolerence to the dot clock check.
>
> Why do you think this shouldn't be merged ?
It pisses of a lot of people who really insist upon accurate timing. I
think a better fix would be to have a dotclock range in drm_panel, and
some magic to figure out which one of these we can actually do. Then
tell userspace that this is the mode is should request. That way
userspace knows what the actual dotclock/refresh rate is, and the
panel still works.
-Daniel
>
> > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>
> > ---
> > drivers/gpu/drm/sun4i/sun4i_rgb.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
> > b/drivers/gpu/drm/sun4i/sun4i_rgb.c index bf068da6b12e..23bdc449eacc 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
> > @@ -92,13 +92,14 @@ static enum drm_mode_status sun4i_rgb_mode_valid(struct
> > drm_encoder *crtc,
> >
> > DRM_DEBUG_DRIVER("Vertical parameters OK\n");
> >
> > + /* Check against a 5% tolerance for the dot clock */
> > tcon->dclk_min_div = 6;
> > tcon->dclk_max_div = 127;
> > rounded_rate = clk_round_rate(tcon->dclk, rate);
> > - if (rounded_rate < rate)
> > + if (rounded_rate < rate * 19 / 20 )
> > return MODE_CLOCK_LOW;
> >
> > - if (rounded_rate > rate)
> > + if (rounded_rate > rate * 21 / 20)
> > return MODE_CLOCK_HIGH;
> >
> > DRM_DEBUG_DRIVER("Clock rate OK\n");
>
> --
> Regards,
>
> Laurent Pinchart
>
>
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
