On 09-10-18, 10:40, Pierre Yves MORDRET wrote: > > > On 10/07/2018 06:00 PM, Vinod wrote: > > On 28-09-18, 15:01, Pierre-Yves MORDRET wrote: > >> This patch adds support of DMA/MDMA chaining support. > >> It introduces an intermediate transfer between peripherals and STM32 DMA. > >> This intermediate transfer is triggered by SW for single M2D transfer and > >> by STM32 DMA IP for all other modes (sg, cyclic) and direction (D2M). > >> > >> A generic SRAM allocator is used for this intermediate buffer > >> Each DMA channel will be able to define its SRAM needs to achieve chaining > >> feature : (2 ^ order) * PAGE_SIZE. > >> For cyclic, SRAM buffer is derived from period length (rounded on > >> PAGE_SIZE). > > > > So IIUC, you chain two dma txns together and transfer data via an SRAM? > > Correct. one DMA is DMAv2 (stm32-dma) and the other is MDMA(stm32-mdma). > Intermediate transfer is between device and memory. > This intermediate transfer is using SDRAM. Ah so you use dma calls to setup mdma xtfers? I dont think that is a good idea. How do you know you should use mdma for subsequent transfer? > >> drivers/dma/stm32-dma.c | 879 ++++++++++++++++++++++++++++++++++++++++++------ > > > > that is a lot of change for a driver, consider splitting it up > > logically in smaller changes... > > > > This feature is rather monolithic. Difficult to split up. > All the code is required at once. It can be enabled at last but split up logically. Intrusive changes to a driver make it hard to review.. -- ~Vinod
