Hi Marc, On mar., oct. 02 2018, Marc Zyngier <marc.zyngier@xxxxxxx> wrote: > On Mon, 01 Oct 2018 15:13:44 +0100, > Miquel Raynal <miquel.raynal@xxxxxxxxxxx> wrote: >> >> The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired >> inputs. Its purpose is to aggregate all CP interrupts and report them to >> the AP through MSIs. The ICU writes into GIC registers (AP side) by way >> of the interconnect. These interrupts can be of several groups: >> - SecuRe (SR); >> - Non-SecuRe (NSR); >> - System Error Interrupts (SEI); >> - RAM Error Interrupts (REI); >> - ... >> Each ICU wired interrupt can be of any of these groups. The group is >> encoded in the MSI payload. > > [...] > > I'm now ready to queue patches 1 through to 11 (with patches 6 and 9 > as of v7). Who is picking up the DT patches (12 to 14)? I will do it. Thanks, Gregory > > Thanks, > > M. > > -- > Jazz is not dead, it just smell funny. -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
