Hi Hugues, On Thu, Sep 27, 2018 at 04:46:06PM +0200, Hugues Fruchet wrote: > This optional property aims to inform parallel video devices > of the maximum pixel clock frequency admissible by host video > interface. If bandwidth of data to be transferred requires a > pixel clock which is higher than this value, parallel video > device could then typically adapt framerate to reach > this constraint. > > Signed-off-by: Hugues Fruchet <hugues.fruchet@xxxxxx> > --- > Documentation/devicetree/bindings/media/video-interfaces.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt > index baf9d97..fa4c112 100644 > --- a/Documentation/devicetree/bindings/media/video-interfaces.txt > +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt > @@ -147,6 +147,8 @@ Optional endpoint properties > as 0 (normal). This property is valid for serial busses only. > - strobe: Whether the clock signal is used as clock (0) or strobe (1). Used > with CCP2, for instance. > +- pclk-max-frequency: maximum pixel clock frequency admissible by video > + host interface. Is there a limit on the pixel clock or the link frequency? We do have a property for the link frequency and a control for the pixel lock as well as for the link frequency. Could these be used for the purpose? The link frequency in general should be specified for the board, and that limits the pixel clock as well in the case the bus transfers a given number of pixels per clock. The OMAP3ISP driver also address this by reading back the pixel clock from the sensor before starting streaming. -- Regards, Sakari Ailus e-mail: sakari.ailus@xxxxxx
