From: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx> Add the phandle, address, size and ranges to the Stratix10 System Manager node to match the existing Arria10 EDAC implementation. Signed-off-by: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx> Acked-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> --- v2 No change --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index d033da401c26..78b4b06e8935 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -469,9 +469,13 @@ eccmgr { compatible = "altr,socfpga-s10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; interrupts = <0 15 4>, <0 95 4>; interrupt-controller; #interrupt-cells = <2>; + ranges; sdramedac { compatible = "altr,sdram-edac-s10"; -- 2.7.4